The present invention relates to a method of manufacturing a semiconductor device. For example, the invention is usable for manufacturing a semiconductor device having a bipolar transistor.
Each of transistors to be used for current amplification has an amplification factor (hFE) having a value corresponding to a specification of the transistor. As a method of suppressing variations in amplification factor hFE characteristics between a plurality of transistors formed from one semiconductor wafer in a manufacturing process of a semiconductor device, it is known that a vertical furnace is used instead of a horizontal furnace in a heat treatment step for diffusing an impurity introduced into a semiconductor substrate.
Japanese Unexamined Patent Application Publication No. Hei 5(1993)-67739 describes that part of a surface of a semiconductor wafer is covered with a mask, and emitter regions of some transistors are modified crystallographically or metallurgically, thereby the amplification factor hFE of each of such transistors is varied.